(a) Field of the Invention
The present invention relates to a method for forming a Cu interconnect pattern and, more particularly, to a technique for forming a Cu interconnect pattern having a higher reliability and a higher density on a zinc oxide film in a printed circuit board, semiconductor device, LCD panel etc.
(b) Description of the Related Art
The conventional techniques for forming a Cu interconnect pattern on a zinc oxide film overlying a substrate of a printed circuit board, such as ceramic substrate, glass substrate, silicon wafer substrate and organic resin substrate, include subtractive process, semi additive process, and additive process.
Each of the processes as mentioned above includes the steps of forming a zinc oxide (ZnO) film overlying a substrate, forming a metallic catalyst film including tetravalent tin ions and divalent palladium ions on the ZnO film to activate the ZnO film by the metallic catalyst film.
The subtractive process is reported by H. Yoshiki, K. Hashimoto, and A. Fujisima in xe2x80x9cElectroless Copper Plating Using ZnO Thin Film Coated on a Glass Substratexe2x80x9d, J. Electrochem. Soc., Vol. 141, No.5, May 1994.
The subtractive process includes, in addition to the steps as mentioned above, the steps of plating the ZnO film with a Cu interconnect film by using an electroless plating (chemical plating) technique or a combination of consecutive electroless plating and electrolytic plating (panel plating) techniques, forming a temporary plating resist film on the Cu interconnect film by a coating or bonding process, patterning the resist film to leave a portion of the resist film as a masking film, and wet-etching a portion of the Cu interconnect film not covered by the masking film while using a suitable etchant, to form a Cu interconnect pattern.
The semi additive process includes, in addition to the steps as mentioned above, the steps of plating the ZnO film with a thin metallic seed film by using an electroless plating technique, forming a plating resist film by coating on the metallic seed film, patterning the plating resist film to form trenches in the plating resist film for exposing the metallic seed film, and depositing a metallic interconnect pattern on the metallic seed film in the trenches by an electrolytic plating technique using the metallic seed film as a cathode for the plating.
The semi additive technique further includes the steps of removing the plating resist film by a solvent, and etching an exposed portion of the metallic seed film not covered by the plating metallic film to thereby leave the metallic interconnect pattern.
The additive technique includes, in addition to the above mentioned steps, forming a permanent plating resist film on the metallic catalyst film by coating, patterning the permanent plating resist film to form trenches therein, and forming an interconnect pattern by an electroless plating technique within the trenches to form a Cu interconnect pattern.
FIGS. 1A to 1F show the conventional additive process. In FIG. 1A, a ZnO film 42 is formed on a substrate 41, followed by forming a Pb catalyst film 43 thereon, as shown in FIG. 1B. Subsequently, a permanent plating resist film is formed thereon by coating, followed by consecutive curing and development thereof to form a desired pattern on the permanent plating resist film 44, as shown in FIG. 1C, wherein a plurality of trenches 400 each for receiving an interconnect line are formed in the permanent plating resist film 44.
The resultant board 40 is then dipped in an accelerator 45 for activation of the Pb catalyst film 43, as shown in FIG. 1D. The board 40 is then dipped in a high-speed electrolytic additive plating liquid 46 for plating, as shown in FIG. 1E. Thus, a final board 50 is obtained wherein a plating Cu film pattern 47 overlies a ZnO film 42 formed on a substrate 41, as shown in FIG. 1F. Although a printed circuit board generally mounts thereon a plurality of Cu interconnect patterns, only the case of a single Cu interconnect pattern being mounted by the circuit board is described in this text for the purpose of simplification of the description.
Patent Publication JP-A-7-321111 describes another method using an electroless plating technique and reduction of ZnO for forming a Cu interconnect pattern. In the publication, a metallic film is first formed by dipping a board mounting thereon a ZnO film in an aqueous solution wherein a metal having a lower ionization tendency compared to ZnO is solved, followed by electrolytic plating or electroless plating the metallic film with another metal to form an interconnect pattern. In the dipping process, the ZnO film is replaced by the metallic film as a conductive film by reduction-depositing the metal in the aqueous solution on the board while solving the ZnO film in the aqueous solution by using the principle of the electroless plating.
Another conventional technique for forming a Cu interconnect pattern uses photo-catalytic property of ZnO wherein a resist film is not used for patterning of a conductive layer by using a ultraviolet exposure process while using a photo-mask. This technique uses the photo-catalytic property of ZnO known as a semiconductive oxide. The process includes the steps of dipping a substrate mounting thereon a 1-xcexcm-thick ZnO film in an aqueous solution including palladium chloride (II) to allow the ZnO film to adsorb divalent palladium ions (Pd2+), and exposing the resultant ZnO film to a ultraviolet ray by using a photo-mask to generate a photo-catalytic reaction in the ZnO film, whereby the palladium ions are reduced or deoxidized in the area of ultraviolet radiation to metallic palladium (Pd).
In the photo-catalytic reaction as described above, electrons in the valence band absorb ultraviolet ray to be excited and enter the conduction band. The excited electrons are then taken out from the surface of the ZnO film to cause the reduction reaction. In the described case, the excited electrons are consumed while reducing the palladium ions to metallic palladium.
The positive holes generated in the valence band by the photo-excitation are taken out from the surface of the ZnO film, similarly to the excited electrons, to cause oxidation reaction. In the described case, the positive holes are consumed while oxidizing the methanol and ethanol to aldehydic materials such as formaldehyde and acetaldehyde.
In an alternative process, the board is dipped in a pH-controlled mixture of aqueous solution of palladium chloride (II) and methanol or ethanol, and subjected to exposure to a ultraviolet ray by using a photo-mask to induce a photo-catalytic reaction of ZnO film, whereby the adsorption of palladium ions onto the surface of the ZnO film and selective reduction of palladium ions to metallic palladium are concurrently proceeded.
The board mounting thereon adsorbed palladium ions and metallic palladium is dipped in a pH-controlled aqueous solution of ethylenediamine (EDA), which has a function of forming chelate, to remove unnecessary palladium ions as EDA chelate. Thus, only the metallic palladium, which has a catalytic function for effecting electroless plating, is selectively left on the surface of the ZnO film.
The resultant board is then dipped in an electroless Cu plating liquid, whereby Cu is deposited on the metallic palladium, which functions as a catalytic core, to form an electroless-plating Cu film. Although the film thickness is small, the Cu interconnect pattern is formed without using a photoresist.
JP-A-9-260808 describes another technique wherein a board mounting thereon a specific film, which has a photo-catalytic function and an increased photosensitivity due to an additive pigment, is dipped in a metallic-ion-containing aqueous solution including at least alcohol, while drawing a pattern on the board with laser having a wavelength corresponding to the absorption band of the pigment. The resultant board is then dipped in an aqueous solution having a function for forming chelate, to thereby remove absorbed metallic ions. Thus, a patterned metallic film having therein absorbed metallic atoms is obtained.
JP-A-10-043589 describes another technique wherein ZnO is used as a photo-catalyst while irradiating a ultraviolet ray to accelerate the reaction.
JP-A-10-245682 describes another technique wherein a board is dipped in an aqueous solution containing zinc nitrate and a reducing agent, while selectively irradiating the light having energy higher than the optical bandgap of ZnO to thereby form an interconnect pattern including ZnO on a board.
In the conventional techniques for forming an interconnect pattern on a ZnO film, the Cu interconnect layer is generally formed by electroless Cu plating using an aqueous solution having a function of forming a chelate, after a metallic catalyst is provided onto the ZnO film. That is, these techniques include the additional step for providing the metallic catalyst to the zinc oxide film, and thus increase the number of steps in the process.
In addition, in the additive technique as described above, it is liable that the metallic catalyst adsorbed on the ZnO film generally remains on the ZnO film in the final product and degrades the insulation between interconnects in the final product.
It is recited in JP-A-7-321111 that a reduction reaction of the oxide to metallic copper proceeds in the plating liquid during the electroless plating process using the reduction reaction of the ZnO film. However, the reduction reaction is not obtained unless an aqueous solution having a higher reduction function, such as an aqueous solution of hydrogenated boron sodium, is used.
In the techniques described in JP-A-9-260808, JP-A-10-043589 and JP-A-10-245682 wherein the photo-catalytic function of ZnO is used, a significant amount of light energy is absorbed in the solution in which irradiation is conducted and it is difficult for the irradiated light to reach the boundary of the reaction.
It is therefore an object of the present invention to provide a method for forming a Cu interconnect pattern having a higher insulation resistance and a higher density on a board.
The present invention provides, in a first aspect thereof, a method including the steps of forming a zinc oxide film overlying a substrate, forming a permanent plating resist film on the zinc oxide film, patterning the permanent plating resist film to form a trench therein for exposing the zinc oxide film, dipping the exposed zinc oxide film in an aqueous solution of copper sulfate to deposit a copper oxide film in the trench by replacing zinc in the exposed zinc oxide film by copper in the copper sulfate, dipping the copper oxide film in a reducing solution to reduce copper oxide in the copper oxide film to metallic copper-to form a metallic copper film in the trench, dipping the metallic copper film in a plating liquid to form a plating copper film on the metallic copper film in the trench.
The present invention provides, in a second aspect thereof, a method including the steps of forming a zinc oxide film overlying a substrate, dipping the zinc oxide film in an aqueous solution of copper sulfate to deposit a copper oxide film by replacing zinc in the zinc oxide film by copper in the copper sulfate, dipping the copper oxide film in a reducing solution to reduce copper oxide in the copper oxide film to metallic copper to form a metallic copper film, dipping the metallic copper film in a plating liquid to form a plating copper film on the metallic copper film, and patterning the metallic copper film and the plating copper film to form a copper interconnect pattern.
In accordance with the method of the present invention, the metallic copper film can be formed on the zinc oxide film by reducing the copper ions to metallic copper by using the reducing solution after the copper ions in the copper sulfate replace the zinc in the zinc oxide film. Thus, the metallic copper film can be plated by a plating copper film in a plating liquid to form a copper interconnect layer having a high insulation resistance and a high density without using plating catalyst, thereby reducing the number of steps in the process.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.